| PART |
Description |
Maker |
| AD802 AD800 AD800-52BR AD800-45BQ AD802-155BR AD80 |
Clock Recovery and Data Retiming Phase-Locked Loop
Clock Recovery and Data Retiming Phase-Locked Loop PHASE LOCKED LOOP, PDSO20
Clock Recovery and Data Retiming Phase-Locked Loop(时钟恢复和重定时PLL)
AD800/AD802: Clock Recovery and Data Retiming Phase-Locked Loop Data Sheet (Rev. B. 12/93)
45 or 52 Mbps Clock and Data Recovery IC
|
Analog Devices, Inc.
|
| W9725G6KB25A W9725G6KB-25 W9725G6KB-18 W9725G6KB-3 |
DLL aligns DQ and DQS transitions with clock, Data masks (DM) for write data, Write Data Mask
|
Winbond
|
| M13S2561616A-2A |
Double-data-rate architecture, two data transfers per clock cycle
|
Elite Semiconductor Mem...
|
| W9751G6KB-18 W9751G6KB-25 W9751G6KB-3 W9751G6KB25A |
Double Data Rate architecture: two data transfers per clock cycle
|
Winbond
|
| W9412G2IB W9412G2IB4 W9412G2IB-6I |
1M × 4 BANKS × 32 BITS GDDR SDRAM
Double Data Rate architecture; two data transfers per clock cycle
4M X 32 DDR DRAM, 0.7 ns, PBGA144
|
Winbond
WINBOND ELECTRONICS CORP
|
| AD807 AD807-155BR AD807A-155BR AD807-155BR-REEL AD |
Fiber Optic Receiver with Quantizer and Clock Recovery and Data Retiming
Fiber Optic Receiver with Quantizer and Clock Recovery and Data Retiming(带数字转时钟恢复和重定时功能的光纤接收器)
Fiber Optic Receiver with Quantizer and Clock Recovery and Data Retiming ATM/SONET/SDH SUPPORT CIRCUIT, PDSO16
|
http://
Analog Devices, Inc.
ANALOG DEVICES INC
|
| SY100ELT21LZG-TR |
Clock and Timing - Clock and Data Distribution
|
Microchip
|
| SY58016LMG |
Clock and Timing - Clock and Data Distribution
|
Microchip
|
| SY58620LMG SY58620LMG-TR |
Clock and Timing - Clock and Data Distribution
|
Microchip
|
| SY58611UMG |
Clock and Timing - Clock and Data Distribution
|
Microchip
|
